(1) Field of the Invention
The present invention relates, in general, to electrical connections to semiconductor devices, and more particularly to an improved bonding pad for bonding an Al wire thereto, and the method of forming the connection.
(2) Description of the Prior Art
Wire bonding has been widely used in the semiconductor industry to electrically connect device terminals, i.e. bonding pads, to terminals on associated devices, and also terminals on supporting package structures. The ends of the wires are connectionally fused to bonding pads by thermocompression bonding where localized heating at the wire--pad interface is promoted by very rapidly moving the wire to generate heat by friction. This heating causes localized melting and subsequent fusion of the pad and wire. As the degree of microminiaturization of semiconductor devices increased, the bonding pads became smaller, more numerous on the device, and more closely spaced. This increased the stress per unit area that is applied to the bonding pad during the bonding operation and also the thermal stress applied as the device temperatures fluctuates during operation. In addition automated bonding apparatus for bonding wires operate at increasingly higher speeds which increase the stress applied to the pad through the wire. When Au wires are used, the present bonding pad technology appears to be adequate to handle the stress. However, gold (Au) is expensive. With the increased emphasis on cost control of integrated circuit semiconductor devices, and the associated package structure, the use of wires made of less expensive metal becomes very important and desirable. Aluminum (Al) wires, which is less expensive than Au wire, has been used for electrical connections. However, the use of Al wires impose greater stress due primarily to its greater coefficient of expansion on the thermal bonding pads resulting in drastically reduced yield. The terminal failure seems to occur most frequently during thermal cycling. The terminal bonding pad separates from the support surface, or at the interfocus of various metal layers of the pad.
The separation of the bonding pad from the substrate is illustrated in FIG. 2. The bonding wire 39, typically aluminum, is bonded to an aluminum or aluminum alloy layer 38, which is in turn bonded to a barrier layer 37, typically a refractory metal layer such as titanium nitride, titanium/tungsten, or titanium. The barrier layer 37 is initially bonded to an insulating layer 36, typically borophosphosilicate glass (BPSG), which in turn is bonded to layer 12, typically silicon oxide. As indicated in FIG. 2 the wire 39 can peel away the underlying pad causing a potential connection failure. The failure may occur immediately during the thermal cycle of the package process (for example during a high temperature molding process). Any thermal cycling may cause large stress and the resultant peeling failure. The poor package yields show that the package thermal cycling process causes the peeling during the high temperature molding process.
In the fabrication of VLSI circuits, a diffusion barrier layer, such as titanium/titanium nitride:tungsten (Ti/TiN:W), has been widely introduced between aluminum alloy and silicon contact to avoid the abnormal interfacial diffusion and increase the circuit lifetime. However, an unstable compound of titanium silicon oxide (TiSixOy) is normally formed between Ti layer and underlying dielectric, e.g. BPSG (borophosphosilicate glass). This unstable compound has poor adhesion to the underlying BPSG and always results in bad bonding yield of the connection from circuit pad to device.
In order that the disadvantage of the above-mentioned conventional technique can be better understood, the process of fabricating conventional VLSI circuits is described hereinafter with reference to FIGS. 1a to 1e.
Referring now to FIG. 1a, a Si substrate 10 is laterally isolated with a field oxide 12 with a thickness of 3000 to 8000 Angstroms by using for example LOCOS (Local Oxidation of Silicon) technology so that an active region is formed on the Si substrate 10. The isolation region, i.e. the field oxide 12, may be formed by other conventional methods understood by those skilled in this art, for example by the trenched dielectric method. After the isolated field oxide 12 is formed, a gate oxide layer 14 is formed over the active region and a doped polysilicon or polycide layer deposited. The layers are etched to form the gate oxide 14 and gate electrode 16. Thereafter, the N+ (or P+) source/drain regions 18 are formed by implanting with suitable impurities. In some VLSI circuits, lightly doped drain (LDD) or double diffused drain (DDD) structures or the like are used.
The next step may be seen with reference to FIG. 1b where a premetal dielectric SiO.sub.2 layer 20, typically borosilicate glass (BSG) or borophosphosilicate glass (BPSG) with a thickness of between about 3000 to 10,000 Angstroms is deposited followed by a high temperature densification. The densification involved placing wafers in a high temperature ambient to make the deposited premetal dielectric SiO.sub.2 layer 20 densified and stable. Metal contact windows 22 are then formed on the densified premetal dielectric SiO.sub.2 layer 20 by dry and/or wet etching.
The next step is shown in FIG. 1c wherein diffusion barrier layers TiN 24/TiSi.sub.2 26 are formed on the metal contact windows 22, and TiN 24/TiSixOy 28 layers are formed on the premetal dielectric SiO.sub.2 layer 20. The formation of diffusion barrier layer is completed by sputtering Ti, followed by rapid thermal annealing in a nitrogen atmosphere to form the TiSi.sub.2 and TiSixOy layers adjacent the source/drain regions 18 and on the dielectric layer 20, respectively, and the TiN layer in those portions in contact with the nitrogen atmosphere. Alternatively, the diffusion barrier layer can be formed by sputtering a bi-layered structure of Ti and TiN, or Ti and Ti:W, followed by the same rapid thermal annealing.
Referring now to FIG. 1d, a metal layer 30 is deposited on the surface of the substrate such as Al-Si(0-2%)-Cu(0.5-4%) (aluminum silicon copper) with a thickness of about 4000 to 10000 Angstroms. The metal layer 30 is then patterned using conventional lithography and etching techniques to form the patterns as shown in the drawing.
The final step involves depositing a passivation layer 32, typically SiO.sub.2 and Si.sub.3 N.sub.4 layers with a total thickness of about 5000 to 20000 Angstroms by chemical vapor deposition (CVD), patterning and then forming a pad area 34 by masking and etching the passivation layer 32. The finished VLSI circuit is shown in cross section FIG. 1e.
According to the above conventional technique for fabricating VLSI circuits, the presence of the diffusion barrier layers 24 and 26 is used to get rid of aluminum spiking and silicon precipitate on contacts 22. Al-Si-Cu alloys are used as the metal layer 30 for the purpose of solving the aluminum spiking problem. However, using Al-Si-Cu alloys always results in an excessive amount of Si precipitation on the surface of the Si substrate 10 underlying the metal contact windows 22, then increasing the resistivity thereof. Moreover, with the scaling down of the device dimensions in VLSI circuits, it is desired to increase the stepcoverage of the metal layer of metal contact windows 22, and thus a higher sputtering temperature may be used. This will worsen the silicon precipitation problem. In order to solve the above problem, diffusion barrier layers of TiN 24/TiSi.sub.2 26 are formed on metal contact windows 22. However, this step also forms a unstable TiSixOy layer 28 on premetal dielectric SiO.sub.2 layer 20. As this unstable layer 28 exhibits poor adhesion to the underlying premetal dielectric SiO.sub.2 layer 20, it results in bad pad bonding yields when wire (not shown) to pad 30 is bonded.
U.S. Pat. No. 4,600,658 to Anderson et al, describes a bonding pad for semiconductor device that uses a barrier layer. U.S. Pat. No. 4,800,177 to Nakamae and U.S. Pat. No. 5,057,447 to Paterson also illustrate device structure that use various configurations of bonding pads.
Copending and commonly assigned U.S. patent application Ser. No. 08/207,559, filed Mar. 7, 1994, describes a solution for the same problem addressed by this application. However, the terminal bonding pad and method differ from the bonding pad and method of this application.